Detecting Over Rejection in Testing of Integrated Circuits - ASQ

Detecting Over Rejection in Testing of Integrated Circuits

In parallel testing of integrated circuits (IC's), IC's which are conforming in terms of electrical functionality are sometimes incorrectly rejected. This is commonly known as over rejection. Over rejection is due to faulty sockets or failed components of the test hardware system associated with the socket locations. In this paper we propose a two-stage procedure for monitoring socket locations causing an over rejection: in stage one, a binomial test of proportions is used to identify socket locations which are causing an over rejection; in stage two, a cumulative sum scheme is used to monitor the socket locations to detect possible failures of components of the test hardware system. Detection of faulty sockets or failed components results in a reduction of rejected conforming IC's. A simple method is provided for the design of such a procedure. Formulas are also provided which allow the performance of the scheme to be evaluated. An application of the procedure in parallel testing of IC's is performed. A follow up study is conducted to determine practical problems with the procedure and to find solutions.

Key Words: Bernoulli Distribution, Binomial Distribution, Cumulative Sum Control Charts, Statistical Process Control.

By T. C. Chang, Infineon Technologies Integrated Circuits, Melaka 75914, Malaysia and F. F. Gan, National University of Singapore, Singapore 117543, Republic of Singapore

Introduction

The manufacturing of integrated circuits (IC's) involves wafer fabrication, assembly, and an electrical testing operation. In the electrical testing operation, the functionality of IC's based on electrical measurements is tested by automatic test equipment (tester). This step is extremely important in ensuring that the electrical functionality of IC's is within the specification limits before IC's are shipped to customers. Basically, a tester consists of a test program and a test hardware system. The test hardware system serves as an interface between the IC's being tested and the test program. For memory IC testing parallel testing is routinely used. Each of the IC's in a batch will be contacted with a socket on a specific location in the tester before being tested simultaneously.

In the testing operation IC's which are conforming in terms of electrical functionality are occasionally rejected (commonly known as an over rejection) due to faulty sockets or failed components (pin-cards, components, change kits, and hifix parts) associated with socket locations. Figure 1 shows a Pareto chart of the types of faulty components causing a socket location to reject conforming IC's. The Pareto chart is constructed based on data collected over the period of a year. The major cause of over rejection is faulty sockets, which comprises about 60% of faulty components. A faulty socket can be due to broken, bent, or contaminated socket pins. The failure of other components, which are classified as components of the test hardware system, constitutes the second major cause. This accounts for about 40% of total faulty components. Experience indicates that, except for pin-card and change kit failures, the failures of all the other components given in Figure 1 will only lead to an over rejection associated with socket locations. For pin-card and change kit failures, it is estimated from past data that there is at most a 5\% chance that more than one socket location will produce an over rejection. Thus, socket locations are almost independent of each other in causing an over rejection of IC's.

The IC's are tested in lots of a few thousand. Each lot is associated with an unknown fraction p0 of electrical rejects which varies significantly from lot to lot. The IC's in each lot are loaded into the sockets in batches of 32 or 64 depending on the number of socket locations in the tester. At the end of testing each lot, the number of IC's tested, n, and the number of rejects, X, associated with each of the socket locations are obtained. Table 1 is a data set consisting of the number of IC's tested and the number of rejects associated with 64 socket locations from one of the lots tested. With the information gathered, a process engineer will want to determine whether the rejects observed in each of the socket locations are genuine electrical rejects or rejects due to problems associated with the socket locations. An appropriate statistical technique is needed here to identify faulty sockets or failed components of the test hardware system in order to reduce rejection of conforming IC's. This will also help to reduce the testing cost, which accounts for more than 20% of the total manufacturing cost.

TABLE 1. Results from Testing the First Lot of IC's: n is the Number of IC's Tested, and X is the Number of Rejects for Each of the 64 Socket Locations in a Tester.

Socket Location n X

1 164 0
2 164 2
3 164 0
4 163 0
5 162 2
6 162 2
7 162 2
8 162 1
9 162 1
10 162 2
11 162 1
12 162 1
13 162 2
14 162 2
15 162 2
16 162 0
17 162 1
18 162 3
19 162 2
20 162 4
21 162 3
22 162 4
23 162 2
24 162 0
25 162 2
26 162 1
27 162 0
28 162 2
29 162 3
30 162 0
31 162 2
32 162 1
33 169 0
34 168 4
35 168 1
36 168 2
37 170 0
38 170 2
39 170 2
40 170 5
41 170 0
42 170 1
43 170 0
44 170 1
45 168 1
46 168 3
47 168 1
48 168 4
49 168 1
50 168 1
51 168 3
52 168 3
53 168 5
54 168 2
55 168 1
56 168 4
57 168 1
58 168 0
59 168 *†8
60 168 2
61 168 2
62 168 3
63 168 5
64 168 5

*Reject the null hypothesis with XA=8 determined based on A=0.0025, average n=165, and p0 is estimated using data from all the socket locations.

†Reject the null hypothesis with XA=8 determined based on A=0.0025, average n=165, and p0 is estimated using data from all the socket locations except socket location number 59.


A two-stage procedure for monitoring socket locations causing an over rejection is developed here. In stage one, a binomial test of proportion based on the number of rejects for each of the socket locations is considered. This test enables a process engineer to identify socket locations that may be causing an over rejection of IC's. Based on the results from stage one, a charting scheme implemented in stage two is used to detect possible failures of components of a test hardware system. The two-stage procedure for parallel testing of IC's is implemented. A follow-up study is then conducted to understand practical problems faced and to fine tune the procedure.

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